12 units
This course examines in depth the theory and practice of fault analysis, test generation, and design for testability for digital ICs and systems. The topics to be covered include circuit and system modeling; fault sources and types; the single stuck-line (SSL), delay, and functional fault models; fault simulation methods; automatic test pattern generation (ATPG) algorithms for combinational and sequential circuits, including the D-algorithm, PODEM, FAN, and the genetic algorithm; testability measures; design-for-testability; scan design; test compression methods; logic-level diagnosis; built-in self-testing (BIST); VLSI testing issues; and processor and memory testing. Advance research issues, including topics on MEMS and mixed-signal testing are also discussed.
4 hrs. lec.
Prerequisites: 18-240 and 15-211 and (18-340 or 18-341). Senior or graduate standing required.
Last updated on May 22, 2007
Computer Hardware
Computer Hardware Engineering
Depth
This course is currently being offered.
F07, F06, F05, F04, S04, S03, S02, F01, F00, F99, F98, F97
Please note that the course history information is incomplete and/or may reflect different courses offered under the same course number.